@inbook{10.1007/978-3-030-58817-5_12,
title = {The Impact of CPU Frequency Scaling on Power Consumption of Computing Infrastructures},
author = {Adriano M Garcia and Matheus Serpa and Dalvan Griebler and Claudio Schepke and Luiz G L Fernandes and Philippe O A Navaux},
editor = {Osvaldo Gervasi and Beniamino Murgante and Sanjay Misra and Chiara Garau and Ivan Ble{č}i{ć} and David Taniar and Bernady O Apduhan and Ana Maria A C Rocha and Eufemia Tarantino and Carmelo Maria Torre and Yeliz Karaca},
doi = {10.1007/978-3-030-58817-5_12},
isbn = {978-3-030-58817-5},
year = {2020},
date = {2020-09-30},
booktitle = {Computational Science and Its Applications -- ICCSA 2020},
pages = {142--157},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {Since the demand for computing power increases, new architectures emerged to obtain better performance. Reducing the power and energy consumption of these architectures is one of the main challenges to achieving high-performance computing. Current research trends aim at developing new software and hardware techniques to achieve the best performance and energy trade-offs. In this work, we investigate the impact of different CPU frequency scaling techniques such as ondemand, performance, and powersave on the power and energy consumption of multi-core based computer infrastructure. We apply these techniques in PAMPAR, a parallel benchmark suite implemented in PThreads, OpenMP, MPI-1, and MPI-2 (spawn). We measure the energy and execution time of 10 benchmarks, varying the number of threads. Our results show that although powersave consumes up to 43.1% less power than performance and ondemand governors, it consumes the triple of energy due to the high execution time. Our experiments also show that the performance governor consumes up to 9.8% more energy than ondemand for CPU-bound benchmarks. Finally, our results show that PThreads has the lowest power consumption, consuming less than the sequential version for memory-bound benchmarks. Regarding performance, the performance governor achieved 3% of performance over the ondemand.},
keywords = {},
pubstate = {published},
tppubtype = {inbook}
}

@article{STEIN:CCPE:20,
title = {Latency‐aware adaptive micro‐batching techniques for streamed data compression on graphics processing units},
author = {Charles M Stein and Dinei A Rockenbach and Dalvan Griebler and Massimo Torquati and Gabriele Mencagli and Marco Danelutto and Luiz G Fernandes},
url = {https://doi.org/10.1002/cpe.5786},
doi = {10.1002/cpe.5786},
year = {2020},
date = {2020-05-01},
journal = {Concurrency and Computation: Practice and Experience},
volume = {na},
number = {na},
pages = {e5786},
publisher = {Wiley Online Library},
abstract = {Stream processing is a parallel paradigm used in many application domains. With the advance of graphics processing units (GPUs), their usage in stream processing applications has increased as well. The efficient utilization of GPU accelerators in streaming scenarios requires to batch input elements in microbatches, whose computation is offloaded on the GPU leveraging data parallelism within the same batch of data. Since data elements are continuously received based on the input speed, the bigger the microbatch size the higher the latency to completely buffer it and to start the processing on the device. Unfortunately, stream processing applications often have strict latency requirements that need to find the best size of the microbatches and to adapt it dynamically based on the workload conditions as well as according to the characteristics of the underlying device and network. In this work, we aim at implementing latency‐aware adaptive microbatching techniques and algorithms for streaming compression applications targeting GPUs. The evaluation is conducted using the Lempel‐Ziv‐Storer‐Szymanski compression application considering different input workloads. As a general result of our work, we noticed that algorithms with elastic adaptation factors respond better for stable workloads, while algorithms with narrower targets respond better for highly unbalanced workloads.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}

@inproceedings{LOFF:ERAD:20,
title = {Implementação Paralela do LU no NPB C++ Utilizando um Pipeline Implícito},
author = {Junior Löff and Dalvan Griebler and Luiz G L Fernandes},
url = {https://doi.org/10.5753/eradrs.2020.10750},
doi = {10.5753/eradrs.2020.10750},
year = {2020},
date = {2020-04-01},
booktitle = {XX Escola Regional de Alto Desempenho da Região Sul (ERAD-RS)},
pages = {37-40},
publisher = {Sociedade Brasileira de Computação (SBC)},
address = {Santa Maria, BR},
abstract = {Neste trabalho, um pipeline implícito com o padrão map foi implementado na aplicação LU do NAS Parallel Benchmarks em C++. O LU possui dependência de dados no tempo, o que dificulta a exploração do paralelismo. Ele foi convertido de Fortran para C++, a fim de ser paralelizado com diferentes bibliotecas de sistemas multi-core. O uso desta estratégia com as bibliotecas permitiu ganhos de desempenho de até 10.6% em relação a versão original.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}

@inproceedings{ARAUJO:ERAD:20,
title = {Implementação CUDA dos Kernels NPB},
author = {Gabriell Alves de Araújo and Dalvan Griebler and Luiz G L Fernandes},
url = {https://doi.org/10.5753/eradrs.2020.10762},
doi = {10.5753/eradrs.2020.10762},
year = {2020},
date = {2020-04-01},
booktitle = {XX Escola Regional de Alto Desempenho da Região Sul (ERAD-RS)},
pages = {85-88},
publisher = {Sociedade Brasileira de Computação (SBC)},
address = {Santa Maria, BR},
abstract = {NAS Parallel Benchmarks (NPB) é um conjunto de benchmarks utilizado para avaliar hardware e software, que ao longo dos anos foi portado para diferentes frameworks. Concernente a GPUs, atualmente existem apenas versões OpenCL e OpenACC. Este trabalho contribui com a literatura provendo a primeira implementação CUDA completa dos kernels do NPB, realizando experimentos com carga de trabalho inédita e revelando novos fatos sobre o NPB.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}

@inproceedings{HOFFMANN:ERAD:20,
title = {Geração Automática de Código TBB na SPar},
author = {Renato Barreto Hoffmann and Dalvan Griebler and Luis G L Fernandes},
url = {https://doi.org/10.5753/eradrs.2020.10765},
doi = {10.5753/eradrs.2020.10765},
year = {2020},
date = {2020-04-01},
booktitle = {XX Escola Regional de Alto Desempenho da Região Sul (ERAD-RS)},
pages = {97-100},
publisher = {Sociedade Brasileira de Computação (SBC)},
address = {Santa Maria, BR},
abstract = {Técnicas de programação paralela são necessárias para extrair todo o potencial dos processadores de múltiplos núcleos. Para isso, foi criada a SPar, uma linguagem para abstração do paralelismo de stream. Esse trabalho descreve a implementação da geração de código automática para a biblioteca TBB na SPar, uma vez que gerava-se código para FastFlow. Os testes com aplicações resultaram em tempos de execução até 12,76 vezes mais rápidos.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}